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Silicon-native AI · FPGA prototypes live now

AI models,
etched into silicon.

ondie builds ASIC and FPGA chips that run models directly on-die — weights hardwired for performance no GPU can match.

Join the waitlistSee the technology
on-diezero memory wallmetal weights
Transformer blocks/On-die attention/Metal weights/Sub-ms tokens/FPGA → ASIC/Zero memory wall/Deterministic/Edge + rack/Transformer blocks/On-die attention/Metal weights/Sub-ms tokens/FPGA → ASIC/Zero memory wall/Deterministic/Edge + rack/Transformer blocks/On-die attention/Metal weights/Sub-ms tokens/FPGA → ASIC/Zero memory wall/Deterministic/Edge + rack/
The architecture

Inference where it belongs — inside the die.

GPUs spend most of their energy moving weights across the memory wall. ondie removes that wall. Models and weights live on the silicon itself, delivering throughput, efficiency, and latency that off-the-shelf hardware can't reach.

01

On-die inference

Models execute inside the chip. No off-chip memory wall, no PCIe bottleneck.

02

Hardcoded weights

Weights burned into metal at fab. Zero load latency, constant throughput.

03

ASIC-class efficiency

Orders of magnitude fewer joules per token than GPU inference.

04

FPGA path today

Prototype on FPGAs now, pin-compatible ASIC tapeout next.

05

Deterministic latency

Fixed pipelines = predictable sub-millisecond token time.

06

Cloud + edge

From rack-scale to on-device, the same on-die architecture scales.

Performance

Throughput, by orders of magnitude.

On-die execution collapses the memory bottleneck. The result is deterministic, near-constant token time — and the efficiency to run the same models at a fraction of the joules.

benchmark
up to 100×throughput

Relative inference throughput vs. commodity GPU (higher is better).

ondie100 tok/ms
On-die, hardcoded weights
GPU (H100)16 tok/ms
Off-chip HBM
CPU1 tok/ms
Commodity silicon

Illustrative projection of target architecture. Tokens/ms normalized to GPU baseline.

Roadmap

From FPGA to metal.

A staged path: prove on FPGAs today, commit to silicon next, then hardcode weights at the fab for full performance.

  1. FPGA prototypes

    Now

    FPGA prototypes running small foundation models. Partner eval program open.

  2. First ASIC tapeout

    2026

    First ASIC tapeout. On-die weights for select transformer blocks.

  3. Hardcoded-weight dies

    2027

    Hardcoded-weight dies. Full models in metal.

  4. Dev kits + cloud API

    Next

    Dev kits + cloud on-die inference API.

silicon is warm · get on it

Build for a world where models are silicon.

Join engineers and investors building the silicon-native AI stack. Early access to eval units and dev kits.

Join the waitlist