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oondie.ai
Early access program

Get early access to on-die inference.

Join engineers and investors building the silicon-native AI stack. Early partners get eval units, architecture briefs, and a first look at FPGA prototypes.

  • ✓FPGA eval partner program — open now
  • ✓On-die architecture briefs under NDA
  • ✓Priority allocation for first ASIC dev kits

No spam. We'll email you only with silicon updates.

Where we are

A staged path to metal.

Join now to ride along: FPGA prototypes today, ASIC tapeout next, hardcoded-weight dies after that.

  1. FPGA prototypes

    Now

    FPGA prototypes running small foundation models. Partner eval program open.

  2. First ASIC tapeout

    2026

    First ASIC tapeout. On-die weights for select transformer blocks.

  3. Hardcoded-weight dies

    2027

    Hardcoded-weight dies. Full models in metal.

  4. Dev kits + cloud API

    Next

    Dev kits + cloud on-die inference API.

Questions

What you might be wondering.

The model and its weights live inside the silicon die itself — not in external memory. Inference never leaves the chip, removing the memory wall and PCIe bottleneck that dominate GPU latency and power.